A) Field of the Invention
The present invention relates to a multi-layer wiring structure, and more particularly to a multi-layer wiring structure having dummy patterns for improving flatness of the surface of a wiring layer.
B) Description of the Related Art
Brief description will be made on a damascene method of forming multi-layer wiring of a semiconductor integrated circuit device. After an interlayer insulating film is formed, wiring trenches and via holes are formed in the interlayer insulating film. A conductive film of copper or the like is formed to fill the via holes and wiring trenches with the conductive film. If necessary, a barrier metal layer is formed to prevent diffusion of copper. The conductive film is polished using chemical mechanical polishing (CMP) to remove an unnecessary region of the conductive film and leave the conductive film only in the via holes and wiring trenches. This process is repeated to form a multi-layer wiring structure.
If the pattern density of a wiring layer is not uniform, the surface flatness after CMP is likely to be degraded. Depending upon the polishing conditions, the area having a low pattern density is polished easier than the area having a high pattern density, so that an erosion is likely to be formed in the area having the low pattern density. The invention disclosed in Japanese Patent Laid-open Publication No. 2003-140319 adopts the structure that dummy patterns are disposed in an area having a low pattern density to make effective pattern densities have nearly uniform values.
Related art is disclosed in U.S. Patent Laid-open Publication No. 2003/39879.
In a semiconductor integrated circuit device having an inductor, if conductive patterns are formed near the inductor, the electric characteristics of the inductor are altered. In order to stabilize the electric characteristics of an inductor, wiring lines are not generally disposed just under the inductor. Further, it is not appropriate to dispose conductive dummy patterns just under an inductor.
The pattern density of an area of a wiring layer under the inductor becomes therefore low so that erosion is likely to be formed in this area. If erosion is formed, a margin of photography lowers. Further, after CMP for leaving wiring of the damascene structure, conductive material is left in some cases in the area where erosion is formed.
These problems occur not only when a functional element formed on an upper layer is an inductor but also when a functional element is formed which does not allow a conductive pattern to be formed just under the functional element.